MOS transistors have conventionally been used as switching elements in semiconductor integrated circuits, including but certainly not limited to, solid-state image-pickup devices (SSIPDs) as line and image sensors.
FIG. 6 is a schematic diagram showing a representative example of an SSIPD 1 employing MOS transistors as switching elements. The SSIPD comprises an image-pickup field 2 in which multiple pixels (not shown in drawing) are arrayed as a matrix. Each pixel can receive and accumulate light from a photographic object and convert the accumulated light into corresponding signal charges.
Each pixel is usually connected to a horizontal selection line (i.e., a line extending parallel to the output signal line 6 shown and discussed below) and to a respective vertical signal line 4. Each vertical signal line 4 is connected to a source/drain terminal of a respective horizontal-relay MOS transistor 3; the other source/drain terminal of the horizontal-relay MOS transistor is connected to an appropriate output signal line 6. The gate of the horizontal-relay MOS transistor 3 is connected to a horizontal-scanning circuit 5.
The horizontal scanning circuit 5 applies a voltage pulse on the gates of the horizontal-relay MOS transistors 3 to effect ON and OFF control of the horizontal-relay MOS transistors 3. An output terminal 7 associated with each output signal line 6 outputs signal charges to downstream circuitry.
Although six horizontal-relay MOS transistors 3 and six vertical signal lines 4 are shown in FIG. 6, it will be understood that there are a large number of horizontal-relay MOS transistors 3 and vertical signal lines 4 (the number corresponding to the number of pixels aligned in the horizontal direction in the image-pickup field 2, for example, 800).
With respect to each pixel in the image-pickup field 2, a signal corresponding to a signal charge (the signal charge corresponding to an amount of light accumulated by the respective pixel from the photographic object) is relayed via the vertical signal line 4 connected to that pixel to one source/drain terminal of the respective horizontal-relay MOS transistor 3 at a desired pulse timing. When the gate of the horizontal-relay MOS transistor 3 receives a voltage pulse of a desired level from the horizontal scanning circuit 5, the signal at one source/drain terminal of the horizontal relay MOS transistor 3 is transferred to the other source/drain terminal and thus to the output signal line 6. The output signal line 6 outputs the signal from the output terminal 7 to downstream circuitry.
As summarized above, the SSIPD 1 utilizes MOS transistors (horizontal-relay MOS transistors 3) as switching elements. Various performance criteria, such as operating speed, breakdown resistance, etc., are required in MOS transistors. One problem that can affect performance of a MOS transistor is its incidental capacitance. The incidental capacitance of switching elements used in SSIPDs, such as line and image sensors, etc., can seriously affect the entire device, and is considered a critical problem.
For example, in the SSIPD 1 shown in FIG. 6, an incidental capacitance C.sub.s exists on the output signal line 6 side of each horizontal-relay MOS transistor 3. If the number of horizontal-relay MOS transistors 3 aligned in the horizontal direction is N.sub.H, then the overall capacitance C.sub.H of the output signal lines 6 is expressed by Equation (1), below. EQU C.sub.H =(N.sub.H .multidot.C.sub.s)+(Intrinsic capacitance of output signal line 6) (1)
This overall capacitance C.sub.H is "parasitic" in that it serves to lessen the output signal relative to "noise."
In recent years, the number of pixels in SSIPDS, such as line and image sensors, etc., has tended to increase. This increase in the number of pixels aligned in the horizontal direction increases the number N.sub.H of horizontal-relay transistors 3. Consequently, when the number of pixels increases, the overall capacitance C.sub.H of the output signal lines 6 increases, creating the problem of reducing the sensitivity and operating speed of the SSIPD.
FIG. 7 is a cross-section of a representative prior-art normally OFF (enhancement) MOS transistor 10B usable as a switching element (e.g. as the horizontal-relay MOS transistor 3 in FIG. 6). In this MOS transistor 10B, a P-type well field 12 is situated in the main surface of an N-type substrate 11 (e.g., silicon substrate). A P.sup.+ -type contact field 12A, which forms a contact to the P-type well field 12, is situated near the surface of the P-type well field 12. N-type high-concentration fields (termed herein N.sup.+ -type high-concentration fields) 13, 14 are formed near the surface of the well field 12, separated by a desired distance.
One of the N.sup.+ -type high-concentration fields 13, 14 serves as a source field and the other serves as a drain field. But, since the polarity of the N.sup.+ -type high-concentration fields 13, 14 is sometimes reversed when the MOS transistor is used as a switching element, it is not necessarily accurate to always call one or the other of them a source field. However, for the sake of convenience, in order to distinguish the two in the following description, the N.sup.+ -type high-concentration field 13 is referred to as the source field and the N.sup.+ -type high-concentration field 14 is referred to as the drain field.
An insulating (oxide) film 17 comprising, e.g., SiO.sub.2 is formed on the surface of the N-type substrate 11 (including the well field 12), and a gate electrode 15 is formed in the insulating film 17 at a location corresponding to the space between the N.sup.+ -type high-concentration fields 13, 14.
When the MOS transistor 10B is used as a switching element, the respective incidental capacitance C.sub.s presents a significant problem that can lead to reduction in sensitivity and operating speed, as noted above, when this MOS transistor 10B is utilized in a SSIPD.
The incidental capacitance of the MOS transistor 10B is determined by the PN-junction capacitance C.sub.j of the PN junction formed between the source field 13, the drain field 14, and the P-type well field 12.
When the concentration distribution at the junction of the PN junction is approximated by a one-sided step junction, the junction capacitance C.sub.j of the PN junction is expressed by Equations (2) and (3), below. EQU C.sub.j =.epsilon..sub.s /X.sub.d (2) EQU X.sub.d =[2.epsilon..sub.s (V.sub.R +.phi..sub.T)/qC.sub.W ].sup.1/2(3)
The .epsilon..sub.s term in Equations (2) and (3) is the dielectric constant of the semiconductor, X.sub.d is the depletion-layer width, V.sub.R is the reverse-bias voltage applied to the PN junction, .phi..sub.T is the built-in voltage of the PN junction, q is the electronic charge, and C.sub.W is the impurity concentration of the well field 12.
In addition, when silicon is used as the semiconductor substrate material, the dielectric constant .epsilon..sub.s is 11.7.epsilon..sub.0 wherein .epsilon..sub.0 is the dielectric constant in a vacuum. Although .phi..sub.T varies depending on the concentration, it is approximately 1 V at most.
As is clear from Equations (2) and (3), reducing the impurity concentration C.sub.W of the well field 12 or applying a reverse-bias voltage V.sub.R, both increasing the depletion-layer width X.sub.d, is effective in reducing the junction capacitance C.sub.j of the PN junction part.
Given such limitations as the punch-through breakdown resistance of the element, however, it is usually necessary to limit the impurity concentration C.sub.W of the well field 12 to within a specific range, which can make it difficult to reduce C.sub.j drastically. For example, in order to decrease the junction capacitance C.sub.j of the PN junction by half, it is necessary, according to Equations (2) and (3), to reduce the impurity concentration C.sub.W of the well field 12 to one-fourth. This is not practical because of the above-mentioned breakdown limitation.
On the other hand, with respect to the MOS transistor 10B of the prior-art device shown in FIG. 7, it is possible to reduce the PN junction capacitance C.sub.j by widening the depletion layer surrounding the drain and source fields. This is done by applying a reverse-bias voltage V.sub.R at the PN junctions between the P-type well field 12 and each of the source field 13 and the drain field 14. The result is shown in FIG. 8.
In FIG. 8, V.sub.W, V.sub.S, V.sub.D, and V.sub.G indicate the potential (applied voltage) of the well field 12, source field 13, drain field 14, and gate electrode 15, respectively. These potentials V.sub.W, V.sub.S, V.sub.D, V.sub.G change according to the operational status of the device. As explained above, since the polarities of the source and drain fields are sometimes reversed, the source and drain fields cannot be uniformly specified.
By way of example in this discussion, the potential V.sub.G of the gate electrode 15 is 5 V at its logic "high" (when ON) and 0 V at its logic "low" (when OFF). The potential V.sub.S of the source field 13 is always 0 V. The potential V.sub.D of the drain field 14 is the same as or greater than the potential V.sub.S. The potential V.sub.W of the well field 12 is -5 V, which is lower than the potential V.sub.S because of the reverse-bias state of the PN junction between the well field 12 and the source field 13 and drain field 14. Namely, the reverse-bias voltage V.sub.R applied at the PN junctions between the P-type well field 12 and the source field 13 and the drain field 14 is 5 V. (Hereinafter, this reverse-bias voltage is referred to simply as being applied at the PN junctions.) Under such conditions, a depletion layer 20B is formed surrounding the source field 13 and drain field 14 of the MOS transistor 10B (i.e., the width of the depletion layer increases).
Another consequence of the foregoing example is that, from Equations (2) and (3), if .phi..sub.T is 1 V, then the junction capacitance C.sub.j of the PN junction of this MOS transistor 10B is (1/6).sup.1/2 (i.e., 0.4082) times the junction capacitance when the reverse-bias voltage V.sub.R is not applied, thereby more than halving the PN junction capacitance C.sub.j.
Whenever the MOS transistor 10B of FIG. 8 is used as the horizontal-relay MOS transistor 3 in the SSIPD 1 of FIG. 6, the capacitances C.sub.S and C.sub.H can be reduced by placing the PN junctions between the well field 12 and each of the source field 13 and drain field 14 in a reverse-bias state.
Unfortunately, however, whenever a reverse-bias voltage is applied at the PN junction between the source/drain field 13 and the well field 12 in the enhancement-type (normally OFF) MOS transistor 10B, the switching-element conductance (channel conductance) is reduced. This creates a problem of reducing the operating speed of the SSIPD.
The channel conductance g.sub.D of the MOS transistor 10B is expressed by Equation (4), below: EQU g.sub.D =(.DELTA.I.sub.D /.DELTA.V.sub.DS)=(W/L).mu.C.sub.OX (V.sub.GS -V.sub.T) (4)
wherein W denotes the channel width and L denotes the channel length (i.e., distance between the source field 13 and the drain field 14). The amount of shift .DELTA.V.sub.T in the threshold voltage V.sub.T (voltage to switch from ON to OFF or OFF to ON) when a reverse-bias voltage is applied at the PN junction of the MOS transistor 10B (PN junction between the source field 13 and the well field 12) is expressed by Equation (5): EQU .DELTA.V.sub.T =[2q.epsilon..sub.s C.sub.W (V.sub.R +.phi..sub.T) ].sup.1/2 /C.sub.OX -(2q.epsilon..sub.s C.sub.W .phi..sub.T).sup.1/2 /C.sub.OX(5)
wherein C.sub.OX is the gate oxide film capacitance (which is, e.g., 6.9.times.10.sup.-8 F/cm.sup.-2 when (or if) the thickness of the insulating film (oxide film) 17 is 500 .ANG.ngstroms).
Changes in the channel conductance g.sub.D occur, when a reverse-bias voltage V.sub.R (e.g., 5 V) is impressed at the PN junction, as follows, applying Equations (4) and (5). First, the amount of shift .DELTA.V.sub.T in the threshold voltage is found according to Equation (5); .DELTA.V.sub.T is 2.7 V when C.sub.W is 5.times.10.sup.16 cm.sup.-3, V.sub.R is 5 V, .phi..sub.T is 1 V, and .epsilon..sub.s is 11.7.epsilon..sub.O. Consequently, when the threshold voltage before applying the reverse-bias voltage V.sub.R (5 V) is 1 V, the threshold voltage after applying the reverse-bias voltage V.sub.R is 3.7 V (i.e., 1 V+2.7 V).
As is evident from Equation (4), the channel conductance g.sub.D is proportional to (V.sub.GS -V.sub.T). As explained above, since the potential of the gate electrode 15 when ON is assumed to be 5 V, and the potential V.sub.S of the source field 13 is assumed to be always at 0 V during ON operation, V.sub.GS is at 5 V during ON operation. Consequently, as shown above, (V.sub.GS -V.sub.T) changes from 4 V to 1.3 V as the threshold voltage is changed from 1 V to 3.7 V. In other words, the channel conductance g.sub.D, which is proportional to (V.sub.GS -V.sub.T), decreases to approximately 1/3 due to the shift in the threshold voltage V.sub.T.
The reduction in the channel conductance g.sub.D can be suppressed by increasing V.sub.GS. But, in order to increase V.sub.GS, it is necessary to increase the pulse amplitude applied to the gate field 15 (e.g., applying pulse voltages of 0 V (during OFF operation) and 8 V (during ON operation)), or to shift the low-level and high-level values of pulses overall (e.g., applying a pulse voltage of 2.7 V (during OFF operation) and 7.7 V (during ON operation)) depending on the threshold-voltage shift .DELTA.V.sub.T. This is impractical because power consumption is increased or the drive circuit is made more complex.